? semiconductor components industries, llc, 2011 october, 2011 ? rev. 1 1 publication order number: NLSX0102/d NLSX0102 2-bit 20 mb/s dual-supply level translator the NLSX0102 is a 2 ? bit configurable dual ? supply bidirectional auto sensing translator that does not require a directional control pin. the i/o v cc and i/o v l ports are designed to track two different power supply rails, v cc and v l respectively. both the v cc and v l supply rails are configurable from 1.5 v to 5.5 v. this allows voltage logic signals on the v l side to be translated into lower, higher or equal value voltage logic signals on the v cc side, and vice ? versa. the NLSX0102 translator has integrated 10 k pull ? up resistors on the i/o lines. the integrated pull ? up resistors are used to pull ? up the i/o lines to either v l or v cc . the NLSX0102 is an excellent match for open ? drain applications such as the i 2 c communication bus. features ? v l can be less than, greater than or equal to v cc ? wide v cc operating range: 1.5 v to 5.5 v wide v l operating range: 1.5 v to 5.5 v ? high ? speed with 24 mb/s guaranteed date rate ? low bit ? to ? bit skew ? enable input and i/o pins are overvoltage tolerant (ovt) to 5.5 v ? non ? preferential power ? up sequencing ? integrated 10 k pull ? up resistors ? small space saving package ? 1.9 mm x 0.9 mm x 0.5 mm flipchip8 ? this is a pb ? free device typical applications ? i 2 c, smbus ? low voltage asic level translation ? mobile phones, pdas, cameras important information ? esd protection for all pins ? human body model (hbm) > 7000 v marking diagram http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information a1 aag = specific device code a = assembly location y = year ww = work week aag ayww a1 a2 d1 flip ? chip 8 case 499bf pin assignments a1 b1 c1 d1 a2 b2 c2 d2 i/o v cc 2 gnd v l i/o v l 2 i/o v cc 1 v cc en i/o v l 1 v l v cc gnd en i/o v l 1 i/o v l 2 i/o v cc 1 i/o v cc 2 logic diagram (top view)
NLSX0102 http://onsemi.com 2 figure 1. block diagram (1 i/o line) pu1 r pullup 10 k v l i/o v l i/o v cc v cc one ? shot block one ? shot block pu2 gate bias n r pullup 10 k en en pin assignment pins description v cc v cc supply voltage v l v l supply voltage gnd ground en output enable, referenced to v l i/o v cc n i/o port, referenced to v cc i/o v l n i/o port, referenced to v l function table en operating mode l hi ? z h i/o buses connected maximum ratings symbol parameter value condition unit v cc high ? side dc supply voltage ? 0.5 to +7.0 v v l low ? side dc supply voltage ? 0.5 to +7.0 v i/o v cc v cc ? referenced dc input / output voltage ? 0.5 to +7.0 v i/o v l v l ? referenced dc input / output voltage ? 0.5 to +7.0 v v en enable control pin dc input voltage ? 0.5 to +7.0 v i i/o_sc short ? circuit duration (i/o v l and i/o v cc to gnd) 50 continuous ma i i/ok input / output clamping current (i/o v l and i/o v cc ) ? 50 v i/o < 0 ma t stg storage temperature ? 65 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
NLSX0102 http://onsemi.com 3 recommended operating conditions symbol parameter min max unit v cc high ? side positive dc supply voltage 1.5 5.5 v v l low ? side positive dc supply voltage 1.5 5.5 v v en enable control pin voltage gnd 5.5 v v io i/o pin voltage gnd 5.5 v t/ v input transition rise and fall rate i/o v l and i/o v cc ports, push ? pull driving 10 ns/v control input 10 t a operating temperature range ? 40 +85 c dc electrical characteristics (t a = ? 40 to +85 c, unless otherwise specified) symbol parameter test conditions (note 1) v l v cc ? 40 c to +85 c unit min typ (notes 1, 2) max v ihc i/o v cc input high voltage 1.5 to 5.5 1.5 to 5.5 v cc ? 0.4 ? v v ilc i/o v cc input low voltage 1.5 to 5.5 1.5 to 5.5 0.15 v v ihl i/o v l input high voltage 1.5 to 5.5 1.5 to 5.5 v l ? 0.4 ? v v ill i/o v l input low voltage 1.5 to 5.5 1.5 to 5.5 0.15 v v ih control pin input high voltage 1.5 to 5.5 1.5 to 5.5 0.65 * v l ? v v il control pin input low voltage 1.5 to 5.5 1.5 to 5.5 0.35 * v l v v ohc i/o v cc output high voltage i/o v cc source current = ? 20 a 1.5 to 5.5 1.5 to 5.5 2/3 * v cc ? v v olc i/o v cc output low voltage i/o v cc sink current = 1 ma 1.5 to 5.5 1.5 to 5.5 0.4 v v ohl i/o v l output high voltage i/o v l source current = ? 20 a 1.5 to 5.5 1.5 to 5.5 2/3 * v l ? v v oll i/o v l output low voltage i/o v l sink current = 1 ma 1.5 to 5.5 1.5 to 5.5 0.4 v i qvl v l supply current supply current i/o v cc and i/o v l unconnected, v en = v l 1.5 to 5.5 1.5 to 5.5 2.0 a 5.5 0 2.0 0 5.5 ? 1.0 i qvcc v l supply current supply current i/o v cc and i/o v l unconnected, v en = v l 1.5 to 5.5 1.5 to 5.5 2.0 a 5.5 0 2.0 0 5.5 ? 1.0 i ts ? vcc v cc tri ? state output mode i/o v cc and i/o v l unconnected, v en = gnd 1.5 to 5.5 1.5 to 5.5 1.0 a i ts ? vl v l tri ? state output mode supply current i/o v cc and i/o v l unconnected, v en = gnd 1.5 to 5.5 1.5 to 5.5 1.0 a 1. typical values are for v cc = +3.3 v, v l = +1.8 v and t a = +25 c. 2. all units are production tested at t a = +25 c. limits over the operating temperature range are guaranteed by design.
NLSX0102 http://onsemi.com 4 dc electrical characteristics (t a = ? 40 to +85 c, unless otherwise specified) symbol unit ? 40 c to +85 c v cc v l test conditions (note 1) parameter symbol unit max typ (notes 1, 2) min v cc v l test conditions (note 1) parameter i i enable pin input leakage current 1.5 to 5.5 1.5 to 5.5 1.0 a i oz i/o tri ? state output mode leakage current 1.5 to 5.5 1.5 to 5.5 1.0 a r pu pull ? up resistors i/o v l and v c 10 k 1. typical values are for v cc = +3.3 v, v l = +1.8 v and t a = +25 c. 2. all units are production tested at t a = +25 c. limits over the operating temperature range are guaranteed by design. timing characteristics ? rail ? to ? rail driving configuration (i/o test circuits of figures 2, 3 and 7, c load = 15 pf, driver output impedance 50 , r load = 1 m , unless otherwise specified) symbol parameter conditions ? 40 c to +85 c unit v cc = 2.3 to 2.7 v v cc = 3.0 to 3.6 v v cc = 4.5 to 5.5 v min max min max min max v l = 1.65 to 1.95 v t rvl i/o v l rise time figure 8 0.6 9.5 2.3 12.5 0.8 7.6 ns t rvcc i/o v cc rise time figure 8 4.0 10.8 2.7 9.1 2.7 7.6 ns t fvl i/o v l fall time figure 8 2.0 9.7 1.9 8.1 1.7 13.3 ns t fvcc i/o v cc fall time figure 8 2.9 13.8 2.8 16.2 2.8 16.2 ns t phl ? vl ? vcc propagation delay (driving i/o v l , v l to v cc ) figure 2 5.6 7.1 6.8 ns t plh ? vl ? vcc 6.5 7.1 7.4 t phl ? vcc ? vl propagation delay (driving i/o v cc , v cc to v l ) figure 3 4.8 5.3 2.0 ns t plh ? vcc ? vl 4.8 5.0 3.5 t en enable time figure 7 50 40 35 ns t dis disable time figure 7 316 225 215 ns t ppskew part ? to ? part skew 0.7 0.7 0.7 ns mdr maximum data rate 21 22 24 mbps v l = 2.3 to 2.7 v t rvl i/o v l rise time figure 8 2.8 7.7 2.6 8.1 1.8 10.3 ns t rvcc i/o v cc rise time figure 8 3.2 9.2 2.9 8.8 2.4 6.4 ns t fvl i/o v l fall time figure 8 1.9 8.3 1.9 7.8 1.8 7.4 ns t fvcc i/o v cc fall time figure 8 2.2 8.3 2.4 8.0 2.6 10.0 ns t phl ? vl ? vcc propagation delay (driving i/o v l , v l to v cc ) figure 2 3.2 3.7 3.9 ns t plh ? vl ? vcc 4.8 5.3 6.0 t phl ? vcc ? vl propagation delay (driving i/o v cc , v cc to v l ) figure 3 2.5 1.6 1.0 ns t plh ? vcc ? vl 4.5 4.3 3.4 t en enable time figure 7 50 40 35 ns t dis disable time figure 7 225 225 215 ns t ppskew part ? to ? part skew 0.7 0.7 0.7 ns mdr maximum data rate 20 22 24 mbps
NLSX0102 http://onsemi.com 5 timing characteristics ? rail ? to ? rail driving configuration (i/o test circuits of figures 2, 3 and 7, c load = 15 pf, driver output impedance 50 , r load = 1 m , unless otherwise specified) symbol unit ? 40 c to +85 c conditions parameter symbol unit v cc = 4.5 to 5.5 v v cc = 3.0 to 3.6 v v cc = 2.3 to 2.7 v conditions parameter symbol unit max min max min max min conditions parameter v l = 3.0 to 3.6 v t rvl i/o v l rise time figure 8 2.3 6.5 1.9 8.0 ns t rvcc i/o v cc rise time figure 8 2.5 6.5 2.1 7.4 ns t fvl i/o v l fall time figure 8 2.0 7.2 1.9 5.9 ns t fvcc i/o v cc fall time figure 8 2.3 8.0 2.4 9.3 ns t phl ? vl ? vcc propagation delay (driving i/o v l , v l to v cc ) figure 2 2.4 3.1 ns t plh ? vl ? vcc 3.8 3.8 t phl ? vcc ? vl propagation delay (driving i/o v cc , v cc to v l ) figure 3 2.5 2.6 ns t plh ? vcc ? vl 3.6 3.1 t en enable time figure 7 40 35 ns t dis disable time figure 7 225 235 ns t ppskew part ? to ? part skew 0.7 0.7 ns mdr maximum data rate 23 24 mbps timing characteristics ? open drain driving configuration (i/o test circuits of figures 4, 5 and 7, c load = 15 pf, driver output impedance 50 , r load = 1 m , unless otherwise specified) symbol parameter conditions ? 40 c to +85 c unit v cc = 2.3 to 2.7 v v cc = 3.0 to 3.6 v v cc = 4.5 to 5.5 v min max min max min max v l = 1.65 to 1.95 v t rvl i/o v l rise time figure 8 38 340 30 245 22.0 134 ns t rvcc i/o v cc rise time figure 8 34 330 23 218 10.0 120 ns t fvl i/o v l fall time figure 8 4.4 11.1 4.3 12.0 4.2 14.2 ns t fvcc i/o v cc fall time figure 8 6.9 11 7.5 16.2 7.0 16.2 ns t phlvl ? vcc propagation delay (driving i/o v l , v l to v cc ) figure 2 2.3 27 2.4 20.0 2.6 23.0 ns t plhvl ? vcc 45 260 36.0 208 27.0 208 t phlvcc ? vl propagation delay (driving i/o v cc , v cc to v l ) figure 3 1.9 22 1.1 22.0 1.2 22.0 ns t plhvcc ? vl 45.0 200 36 150 27.0 112 t en enable time figure 7 80 70 35 ns t dis disable time figure 7 250 277 290 ns t ppskew part ? to ? part skew 0.7 0.7 0.7 ns mdr maximum data rate 2 2 2 mbps
NLSX0102 http://onsemi.com 6 timing characteristics ? open drain driving configuration (i/o test circuits of figures 4, 5 and 7, c load = 15 pf, driver output impedance 50 , r load = 1 m , unless otherwise specified) symbol unit ? 40 c to +85 c conditions parameter symbol unit v cc = 4.5 to 5.5 v v cc = 3.0 to 3.6 v v cc = 2.3 to 2.7 v conditions parameter symbol unit max min max min max min conditions parameter v l = 2.3 to 2.7 v t rvl i/o v l rise time figure 8 34 400 28.0 300 24.0 208 ns t rvcc i/o v cc rise time figure 8 35.0 352 24.0 280 12.0 180 ns t fvl i/o v l fall time figure 8 4.4 6.9 4.3 6.2 4.2 7.8 ns t fvcc i/o v cc fall time figure 8 4.3 8.8 4.9 9.4 5.4 10.4 ns t phlvl ? vcc propagation delay (driving i/o v l , v l to v cc ) figure 2 1.7 14.0 2.0 14.0 2.1 14.0 ns t plhvl ? vcc 43.0 250 36.0 210 27.0 210 t phlvcc ? vl propagation delay (driving i/o v cc , v cc to v l ) figure 3 1.8 13.0 2.6 13.0 1.2 13.0 ns t plhvcc ? vl 44.0 225 37.0 180 27.0 144 t en enable time figure 7 50 40 35 ns t dis disable time figure 7 265 230 215 ns t ppskew part ? to ? part skew 0.7 0.7 0.7 ns mdr maximum data rate 2 2 2 mbps v l = 3.0 to 3.6 v t rvl i/o v l rise time figure 8 25.0 400 19.0 278 ns t rvcc i/o v cc rise time figure 8 26.0 375 14.0 247 ns t fvl i/o v l fall time figure 8 2.8 6.1 2.6 5.7 ns t fvcc i/o v cc fall time figure 8 2.6 7.6 3.1 8.3 ns t phlvl ? vcc propagation delay (driving i/o v l , v l to v cc ) figure 2 1.3 10.0 1.4 8.0 ns t plhvl ? vcc 36.0 255 28.0 243 t phlvcc ? vl propagation delay (driving i/o v cc , v cc to v l ) figure 3 1.0 124 1.0 97.0 ns t plhvcc ? vl 3.0 185 3.0 136 t en enable time figure 7 40 35 ns t dis disable time figure 7 250 205 ns t ppskew part ? to ? part skew 0.7 0.7 ns mdr maximum data rate 2 2 mbps
NLSX0102 http://onsemi.com 7 test setups NLSX0102 en i/o v l v l v cc c load t rise/fall 3 ns i/o v l i/o v cc t pd_vl ? vcc 90% 50% 10% 90% 50% 10% t pd_vl ? vcc t f ? vcc t r ? vcc figure 2. rail ? to ? rail driving i/o v l i/o v cc NLSX0102 en i/o v l v l v cc c load source t rise/fall 3 ns i/o v cc i/o v l t pd_vcc ? vl 90% 50% 10% 90% 50% 10% t pd_vcc ? vl t f ? vl t r ? vl i/o v cc source figure 3. rail ? to ? rail driving i/o v cc NLSX0102 en i/o v l v l v cc figure 4. open ? drain driving i/o v l i/o v cc NLSX0102 en v l v cc i/o v cc figure 5. open ? drain driving i/o v cc figure 6. definition of timing specification parameters c load v cc c load r load r load r load r load
NLSX0102 http://onsemi.com 8 open pulse generator r t dut v l r l r 1 c l 2 x v* v cc v* = v l or v cc test switch t pzh , t phz open t pzl , t plz 2 x v* c l = 15 pf or equivalent (includes jig and probe capacitance) r l = r 1 = 50 k or equivalent r t = z out of pulse generator (typically 50 ) v* = v l or v cc for i/o_vl or i/o_vcc measurements, respectively. figure 7. test circuit for enable/disable time measurement v cc gnd t f t r 10% 50% 90% 10% 50% 90% t r t plh t phl t f 50% 50% 90% 10% t pzl t plz t pzh t phz gnd high impedance v ol v oh high impedance figure 8. timing definitions for propagation delays and enable/disable measurement en input 50% v l output output output
NLSX0102 http://onsemi.com 9 applications information level translator architecture the NLSX0102 auto sense translator provides bi ? directional voltage level shifting to transfer data in multiple supply voltage systems. this device has two supply voltages, v l and v cc , which set the logic levels on the input and output sides of the translator. when used to transfer data from the v l to the v cc ports, input signals referenced to the v l supply are translated to output signals with a logic level matched to v cc . in a similar manner, the v cc to v l translation shifts input signals with a logic level compatible to v cc to an output signal matched to v l . the NLSX0102 consists of two bi ? directional channels that independently determine the direction of the data flow without requiring a directional pin. the one ? shot circuits are used to detect the rising or falling input signals. in addition, the one shots decrease the rise and fall time of the output signal for high ? to ? low and low ? to ? high transitions. each input/output channel has an internal 10 k pull ? up. the magnitude of the pull ? up resistors can be reduced by connecting external resistors in parallel to the internal 10 k resistors. input driver requirements the rise (t r ) and fall (t f ) timing parameters of the open drain outputs depend on the magnitude of the pull ? up resistors. in addition, the propagation times (t pd ), skew (t pskew ) and maximum data rate depend on the impedance of the device that is connected to the translator. the timing parameters listed in the data sheet assume that the output impedance of the drivers connected to the translator is less than 50 k . enable input (en) the NLSX0102 has an enable pin (en) that provides tri ? state operation at the i/o pins. driving the enable pin to a low logic level minimizes the power consumption of the device and drives the i/o v cc and i/o v l pins to a high impedance state. normal translation operation occurs when the en pin is equal to a logic high signal. the en pin is referenced to the v l supply and has overvoltage tolerant (ovt) protection. power supply guidelines during normal operation, supply voltage v l can be greater than, less than or equal to v cc . the sequencing of the power supplies will not damage the device during the power up operation. for optimal performance, 0.01 f to 0.1 f decoupling capacitors should be used on the v l and v cc power supply pins. ceramic capacitors are a good design choice to filter and bypass any noise signals on the voltage lines to the ground plane of the pcb. the noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the pcb connection traces. ordering information device package shipping ? NLSX0102fct1g flip ? chip 8 (pb ? free) 3000 / tape & reel NLSX0102fct2g flip ? chip 8 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NLSX0102 http://onsemi.com 10 package dimensions 8 pin flip ? chip, 0.9x1.9, 0.5p case 499bf ? 01 issue o seating plane notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. dim a min max 0.44 millimeters a1 b 0.21 0.25 d e 0.50 bsc 0.50 e d a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 8x b 12 b a 0.10 c a a1 c 0.15 0.19 e bottom view side view top view 8x e/2 note 3 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 8x 0.25 a1 0.50 pitch 0.50 pitch package outline e d c e/2 1.90 bsc 0.90 bsc on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. NLSX0102/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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